16 search results - page 3 / 4 » Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
Traditional coherence protocols present a set of difficult tradeoffs: the reliance of snoopy protocols on broadcast and ordered interconnects limits their scalability, while dire...