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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
14 years 1 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
DAC
1997
ACM
14 years 28 days ago
COSYN: Hardware-Software Co-Synthesis of Embedded Systems
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. J...
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
14 years 2 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
JASSS
1998
82views more  JASSS 1998»
13 years 8 months ago
Qualitative modeling and simulation of socio-economic phenomena
This paper describes an application of recently developed qualitative reasoning techniques to complex, socio{economic allocation problems. We explain why we believe traditional op...
Giorgio Brajnik, Marji Lines
DAC
2007
ACM
14 years 9 months ago
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs
Abstract. Embedded multimedia systems often run multiple time-constrained applications simultaneously. These systems use multiprocessor systems-on-chip of which it must be guarante...
Sander Stuijk, Twan Basten, Marc Geilen, Henk Corp...