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    CDES
    2006
    240views Hardware» more  CDES 2006»
    Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
    13 years 10 months ago
    Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
    Download  ww1.ucmss.com
    Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
    Arun N. Chandorkar, Gurvinder Singh
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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    13 years 10 months ago
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    Download  dropzone.tamu.edu
    Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
    Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
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    IJON
    2007
    118views more  IJON 2007»
    Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
    13 years 8 months ago
    Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
    Download  www.ece.neu.edu
    — This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
    Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin ...
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    ISCA
    2010
    IEEE
    205views Hardware» more  ISCA 2010»
    The virtual write queue: coordinating DRAM and last-level cache policies
    14 years 1 months ago
    The virtual write queue: coordinating DRAM and last-level cache policies
    Download  lca.ece.utexas.edu
    In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
    Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
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    GLVLSI
    2008
    IEEE
    190views VLSI» more  GLVLSI 2008»
    A low leakage 9t sram cell for ultra-low power operation
    14 years 3 months ago
    A low leakage 9t sram cell for ultra-low power operation
    Download  www.ece.neu.edu
    This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
    Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
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