A low leakage 9t sram cell for ultra-low power operation

This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it is shown that the 9T cell achieves improvements in power dissipation, performance and stability compared with previous designs (that require 10T and 8T) for low-power operation. The 9T scheme is amenable to small feature sizes as encountered in the deep sub-micron/nano ranges of CMOS technology. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Type and Design Styles – Memory technologies General Terms Performance, Design Keywords SRAM cell, low power, nanotechnology, leakage power, static noise margin

• Type: Conference
• Year: 2008
• Where: GLVLSI
• Authors: Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
• Keywords: Cell Achieves Improvements, GLVLSI 2008, Keywords SRAM Cell, SRAM Cell, VLSI