Sciweavers

    473 search results - page 14 / 95
    » Dynamic Memory Design for Low Data-Retention Power
    Sort
    View
    VLSID
    2005
    IEEE
    139views VLSI» more  VLSID 2005»
    Variable Input Delay CMOS Logic for Low Power Design
    14 years 9 months ago
    Variable Input Delay CMOS Logic for Low Power Design
    Download  www.eng.auburn.edu
    Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
    Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
    claim paper
    Read More »
    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 9 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
    claim paper
    Read More »
    VLSID
    2002
    IEEE
    207views VLSI» more  VLSID 2002»
    Synthesis of High Performance Low Power Dynamic CMOS Circuits
    14 years 9 months ago
    Synthesis of High Performance Low Power Dynamic CMOS Circuits
    Download  www.cs.cmu.edu
    This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
    Debasis Samanta, Nishant Sinha, Ajit Pal
    claim paper
    Read More »
    IPPS
    2009
    IEEE
    176views Distributed And Parallel Com...» more  IPPS 2009»
    Using hardware transactional memory for data race detection
    14 years 3 months ago
    Using hardware transactional memory for data race detection
    Download  www.eecs.umich.edu
    Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
    Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
    claim paper
    Read More »
    ASYNC
    2000
    IEEE
    86views Hardware» more  ASYNC 2000»
    An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
    14 years 1 months ago
    An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
    Download  www.cl.cam.ac.uk
    Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
    George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.