473 search results - page 24 / 95 » Dynamic Memory Design for Low Data-Retention Power |
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the t...
DELTA
2008
IEEE
13 years 10 months ago
2008
IEEE
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
ASPDAC
2007
ACM
14 years 20 days ago
2007
ACM
The development cost of low-power embedded systems can be significantly reduced by reusing legacy designs and applying proper modifications to meet the new power constraints. The ...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
HPDC
2012
IEEE
11 years 11 months ago
2012
IEEE
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...