473 search results - page 26 / 95 » Dynamic Memory Design for Low Data-Retention Power |
126
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DAC
2006
ACM
16 years 3 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
115
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TON
2008
15 years 2 months ago
2008
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
130
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ISCAS
2006
IEEE
15 years 9 months ago
2006
IEEE
Abstract— There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in th...
105
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HIPEAC
2007
Springer
15 years 9 months ago
2007
Springer
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
168
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RTSS
1998
IEEE
15 years 7 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...