473 search results - page 27 / 95 » Dynamic Memory Design for Low Data-Retention Power |
ISVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
CAL
2002
13 years 8 months ago
2002
Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
CODES
2011
IEEE
12 years 8 months ago
2011
IEEE
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...