473 search results - page 59 / 95 » Dynamic Memory Design for Low Data-Retention Power |
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic de...
GI
2004
Springer
14 years 2 months ago
2004
Springer
: Next to authentication, secure key exchange is considered the most critical and complex issue regarding ad-hoc network security. We present a low-cost, (i.e. low hardware-complex...
HIPEAC
2010
Springer
13 years 10 months ago
2010
Springer
The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, a...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...