Sciweavers

473 search results - page 72 / 95
» Dynamic Memory Design for Low Data-Retention Power
Sort
View
IPCCC
2006
IEEE
14 years 2 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
DAC
2006
ACM
14 years 9 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
ISLPED
2009
ACM
184views Hardware» more  ISLPED 2009»
14 years 3 months ago
Online work maximization under a peak temperature constraint
Increasing power densities and the high cost of low thermal resistance packages and cooling solutions make it impractical to design processors for worst-case temperature scenarios...
Thidapat Chantem, Xiaobo Sharon Hu, Robert P. Dick
ICITA
2005
IEEE
14 years 2 months ago
Performance Tuning in the MacauMap Mobile Map Application
With the increasing popularity of mobile computing platforms such as personal digital assistants (PDAs) and smart mobile phones, applications originally designed for higherperform...
Robert P. Biuk-Aghai
CASES
2004
ACM
14 years 14 days ago
Reducing energy consumption of queries in memory-resident database systems
The tremendous growth of system memories has increased the capacities and capabilities of memory-resident embedded databases, yet current embedded databases need to be tuned in or...
Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T...