473 search results - page 77 / 95 » Dynamic Memory Design for Low Data-Retention Power |
EUROPAR
2010
Springer
13 years 9 months ago
2010
Springer
Mutual exclusion locks limit concurrency but offer low latency. Software transactional memory (STM) typically has higher latency, but scales well. In this paper we propose transac...
IEEEPACT
2009
IEEE
14 years 3 months ago
2009
IEEE
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...
ISCAPDCS
2007
13 years 10 months ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
LCTRTS
2007
Springer
14 years 2 months ago
2007
Springer
Energy efficiency is an important factor in embedded systems design. We consider an embedded system with a dynamic voltage scaling (DVS) capable processor and its system-wide pow...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...