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ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
14 years 6 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
ICCD
2005
IEEE
221views Hardware» more  ICCD 2005»
14 years 6 months ago
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
Abstract— Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC ...
Brock J. LaMeres, Sunil P. Khatri
SIGMOD
2009
ACM
161views Database» more  SIGMOD 2009»
14 years 3 months ago
Dependency-aware reordering for parallelizing query optimization in multi-core CPUs
The state of the art commercial query optimizers employ cost-based optimization and exploit dynamic programming (DP) to find the optimal query execution plan (QEP) without evalua...
Wook-Shin Han, Jinsoo Lee
ICS
2009
Tsinghua U.
14 years 3 months ago
Combining thread level speculation helper threads and runahead execution
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
Polychronis Xekalakis, Nikolas Ioannou, Marcelo Ci...
ICPP
2009
IEEE
14 years 3 months ago
Code Semantic-Aware Runahead Threads
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
Tanausú Ramírez, Alex Pajuelo, Olive...
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