1815 search results - page 341 / 363 » Dynamic Power Management Using Data Buffers |
SC
1995
ACM
13 years 11 months ago
1995
ACM
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core micr...
WCNC
2008
IEEE
14 years 2 months ago
2008
IEEE
—1 In ISM bands, many wireless protocols proliferate such as 802.11, Bluetooth, and ZigBee. However, these incompatible protocols create complex coexistence and connectivity prob...
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
KDD
2007
ACM
14 years 8 months ago
2007
ACM
We present DL8, an exact algorithm for finding a decision tree that optimizes a ranking function under size, depth, accuracy and leaf constraints. Because the discovery of optimal...