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» Dynamic Power Management Using Data Buffers
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JEC
2006
71views more  JEC 2006»
13 years 8 months ago
Destructive-read in embedded DRAM, impact on power consumption
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Gran...
DATE
2004
IEEE
132views Hardware» more  DATE 2004»
13 years 11 months ago
Hybrid Architectural Dynamic Thermal Management
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
Kevin Skadron
ICPADS
2006
IEEE
14 years 2 months ago
Destination-Based HoL Blocking Elimination
Congestion management is likely to become a critical issue in interconnection networks, as increasing power consumption and cost concerns will lead to the use of smaller networks....
T. Nachiondo, Jose Flich, José Duato
SAC
2009
ACM
14 years 2 months ago
DARAW: a new write buffer to improve parallel I/O energy-efficiency
In the past decades, parallel I/O systems have been used widely to support scientific and commercial applications. New data centers today employ huge quantities of I/O systems, wh...
Xiaojun Ruan, Adam Manzanares, Kiranmai Bellam, Xi...
VLSID
2003
IEEE
115views VLSI» more  VLSID 2003»
14 years 8 months ago
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
W. Kuang, J. S. Yuan