Sciweavers

669 search results - page 126 / 134
» Dynamic Power Optimization of Interactive Systems
Sort
View
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 3 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
HIPC
2000
Springer
14 years 1 months ago
A Weight Based Distributed Clustering Algorithm for Mobile ad hoc Networks
In this paper, we propose a distributed clustering algorithm for a multi-hop packet radio network. These types of networks, also known as ad hoc networks, are dynamic in nature due...
Mainak Chatterjee, Sajal K. Das, Damla Turgut
IBMRD
2011
112views more  IBMRD 2011»
13 years 5 months ago
Sensor Andrew: Large-scale campus-wide sensing and actuation
—We present Sensor Andrew, a multi-disciplinary campus-wide scalable sensor network that is designed to host a wide range of sensor, actuator and low-power applications. The goal...
Anthony Rowe, Mario Berges, Gaurav Bhatia, Ethan G...
RAM
2008
IEEE
124views Robotics» more  RAM 2008»
14 years 4 months ago
Mechatronics Considerations for Assisting Humans
Mechatronics technologies are now steadily penetrating in our daily lives. We are surrounded by mechatronic products and interact with them in many ways. In particular, mechatroni...
Masayoshi Tomizuka
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 3 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood