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MICRO
2008
IEEE
149views Hardware» more  MICRO 2008»
15 years 8 months ago
Prefetch-Aware DRAM Controllers
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N...
IEEEPACT
2007
IEEE
15 years 8 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
INFOCOM
2007
IEEE
15 years 8 months ago
Queuing Delays in Randomized Load Balanced Networks
—Valiant’s concept of Randomized Load Balancing (RLB), also promoted under the name ‘two-phase routing’, has previously been shown to provide a cost-effective way of implem...
Ravi Prasad, Peter J. Winzer, Sem C. Borst, Marina...
ISSAC
2007
Springer
177views Mathematics» more  ISSAC 2007»
15 years 8 months ago
Component-level parallelization of triangular decompositions
We discuss the parallelization of algorithms for solving polynomial systems symbolically by way of triangular decompositions. We introduce a component-level parallelism for which ...
Marc Moreno Maza, Yuzhen Xie
LCTRTS
2007
Springer
15 years 8 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier