989 search results - page 80 / 198 » Dynamic Symmetry Reduction |
DAC
2007
ACM
15 years 4 days ago
2007
ACM
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
MICRO
2005
IEEE
14 years 4 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
ECCV
2006
Springer
15 years 1 months ago
2006
Springer
Abstract. There has been growing interest in developing nonlinear dimensionality reduction algorithms for vision applications. Although progress has been made in recent years, conv...
DAC
2008
ACM
15 years 4 days ago
2008
ACM
Compared with on-chip routers, the existing commercial tools for off-chip routing have a much lower routability and often result in a large number of unrouted nets for manual rout...
NOSSDAV
2009
Springer
14 years 5 months ago
2009
Springer
Hard-disk drive power consumption reduction methods focus mainly on increasing the amount of time the disk is in standby mode (disk spun down) by implementing aggressive data read...