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» Dynamic Voltage and Cache Reconfiguration for Low Power
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APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
13 years 11 months ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
14 years 27 days ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Low-power techniques for network security processors
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiu...
ISPASS
2010
IEEE
14 years 2 months ago
Performance-effective operation below Vcc-min
Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been prop...
Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet
IPPS
2006
IEEE
14 years 1 months ago
Conjugate gradient sparse solvers: performance-power characteristics
We characterize the performance and power attributes of the conjugate gradient (CG) sparse solver which is widely used in scientific applications. We use cycle-accurate simulatio...
Konrad Malkowski, Ingyu Lee, Padma Raghavan, Mary ...