157 search results - page 17 / 32 » Dynamic Voltage and Cache Reconfiguration for Low Power |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ISPASS
2008
IEEE
14 years 1 months ago
2008
IEEE
Many programs go through phases as they execute. Knowing where these phases begin and end can be beneficial. For example, adaptive architectures can exploit such information to lo...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
ISCAS
2002
IEEE
14 years 8 days ago
2002
IEEE
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...