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HPCA
2009
IEEE
14 years 8 months ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 1 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 1 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
ICS
2009
Tsinghua U.
13 years 12 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
14 years 29 days ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...