Sciweavers

53 search results - page 2 / 11
» Dynamic instruction schedulers in a 3-dimensional integratio...
Sort
View
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
14 years 1 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
IEEEPACT
2007
IEEE
14 years 1 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
MONET
2011
13 years 1 months ago
iDSRT: Integrated Dynamic Soft Real-time Architecture for Critical Infrastructure Data Delivery over WLAN
Critical Infrastructures (CIs) such as the Power Grid play an important role in our lives. Of all important aspects of CIs, real-time data delivery is the most important one becaus...
Hoang Viet Nguyen, Raoul Rivas, Klara Nahrstedt
ICDIM
2010
IEEE
13 years 4 months ago
Simulation integration for healthcare education, training and assessment
Funded as part of the `Network Enabled Platforms' program the Health Services Virtual Organization (HSVO) Project has developed a network-enabled platform (NEP) consisting of...
Rachel H. Ellaway, Jeremy R. Cooperstock, Bruce Sp...
EMSOFT
2005
Springer
14 years 6 days ago
A sink-n-hoist framework for leakage power reduction
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee