329 search results - page 15 / 66 » Dynamic techniques to reduce memory traffic in embedded syst... |
ICCD
1999
IEEE
13 years 12 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
ASYNC
2000
IEEE
14 years 1 days ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the t...
EMSOFT
2007
Springer
14 years 1 months ago
2007
Springer
There is increasing interest in using general-purpose operating systems, such as Linux, on embedded platforms. It is especially important in embedded systems to use memory effici...