329 search results - page 57 / 66 » Dynamic techniques to reduce memory traffic in embedded syst... |
SAMOS
2004
Springer
14 years 25 days ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
HPDC
2012
IEEE
11 years 10 months ago
2012
IEEE
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
CF
2010
ACM
13 years 10 months ago
2010
ACM
Cache memories currently treat all blocks as if they were equally important, but this assumption of equally importance is not always valid. For instance, not all blocks deserve to...