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MICRO
2009
IEEE
113views Hardware» more  MICRO 2009»
14 years 1 months ago
The BubbleWrap many-core: popping cores for sequential acceleration
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
DAC
2010
ACM
13 years 8 months ago
Network on chip design and optimization using specialized influence models
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
Cristinel Ababei
CASES
2006
ACM
14 years 20 days ago
Methods for power optimization in distributed embedded systems with real-time requirements
Dynamic voltage scaling and sleep state control have been shown to be extremely effective in reducing energy consumption in CMOS circuits. Though plenty of research papers have st...
Razvan Racu, Arne Hamann, Rolf Ernst, Bren Mochock...
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
14 years 9 days ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
ISLPED
2007
ACM
57views Hardware» more  ISLPED 2007»
13 years 8 months ago
Resource area dilation to reduce power density in throughput servers
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
Michael D. Powell, T. N. Vijaykumar