40 search results - page 5 / 8 » Dynamic zero compression for cache energy reduction |
ISLPED
2010
ACM
13 years 8 months ago
2010
ACM
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Previous object code compression schemes have employed static and semiadaptive compression algorithms to reduce the size of instruction memory in embedded systems. The suggestion ...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...