130 search results - page 10 / 26 » Dynamically Scheduling VLIW Instructions |
ISCA
1992
IEEE
13 years 11 months ago
1992
IEEE
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
EUROPAR
2005
Springer
14 years 1 months ago
2005
Springer
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
MICRO
2000
IEEE
13 years 12 months ago
2000
IEEE
A machine’s performance is the product of its IPC (Instructions Per Cycle) and clock frequency. Recently, Palacharla, Jouppi, and Smith [3] warned that the dynamic instruction s...
SODA
2001
ACM
13 years 8 months ago
2001
ACM
We consider the problem of scheduling unit-length jobs on identical parallel machines such that the makespan of the resulting schedule is minimized. Precedence constraints impose ...