The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
Andrea Bona, Mariagiovanna Sami, Donatella Sciuto,...
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
Shu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkum...
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...