150 search results - page 4 / 30 » ECO timing optimization using spare cells |
DAC
1997
ACM
14 years 3 months ago
1997
ACM
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
ISMVL
1999
IEEE
14 years 3 months ago
1999
IEEE
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...
GECCO
2005
Springer
14 years 4 months ago
2005
Springer
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with significant run times. Two parallel models for GA are presented for VLSI cell placemen...
DSRT
2008
IEEE
14 years 20 days ago
2008
IEEE
This paper proposes a novel Lightweight Time Warp (LTW) protocol for high-performance parallel optimistic simulation of large-scale DEVS and CellDEVS models. By exploiting the cha...
VLSID
1999
IEEE
14 years 3 months ago
1999
IEEE
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...