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DATE
2000
IEEE
83views Hardware» more  DATE 2000»
14 years 17 days ago
A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper in...
Sungju Park, Taehyung Kim
EURODAC
1995
IEEE
159views VHDL» more  EURODAC 1995»
13 years 11 months ago
The VHDL based design of the MIDA MPEG1 audio decoder
This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL desc...
Andrea Finotello, Maurizio Paolini
CHI
2010
ACM
14 years 1 days ago
Designing games for learning: insights from conversations with designers
This paper presents insights about design practices that can lead to effective and fun games for learning, gleaned from interviews with experienced game developers. We based our a...
Katherine Isbister, Mary Flanagan, Chelsea Hash
DAC
2007
ACM
14 years 9 months ago
Compact State Machines for High Performance Pattern Matching
Pattern matching is essential to a wide range of applications such as network intrusion detection, virus scanning, etc. Pattern matching algorithms normally rely on state machines...
Piti Piyachon, Yan Luo
OOPSLA
2009
Springer
14 years 21 days ago
Overview of the 3rd international workshop on software patterns and quality ((SPAQu'09)
We will discuss here the theoretical, social, technological and practical issues related to quality aspects of software patterns including security and safety aspects. The worksho...
Hironori Washizaki, Nobukazu Yoshioka, Eduardo B. ...