333 search results - page 19 / 67 » EXACT: algorithm and hardware architecture for an improved A... |
ISCAS
2002
IEEE
14 years 1 months ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
SIPS
2008
IEEE
14 years 2 months ago
2008
IEEE
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
SASP
2009
IEEE
14 years 3 months ago
2009
IEEE
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
FCCM
2003
IEEE
14 years 1 months ago
2003
IEEE
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
ICCAD
1998
IEEE
14 years 21 days ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...