Sciweavers

333 search results - page 7 / 67
» EXACT: algorithm and hardware architecture for an improved A...
Sort
View
SIPS
2006
IEEE
14 years 2 months ago
Automated Architectural Exploration for Signal Processing Algorithms
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winse...
DAC
2006
ACM
14 years 9 months ago
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
Eduardo A. C. da Costa, José Monteiro, Leve...
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 8 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
14 years 20 hour ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
CGO
2010
IEEE
14 years 1 months ago
Taming hardware event samples for FDO compilation
Feedback-directed optimization (FDO) is effective in improving application runtime performance, but has not been widely adopted due to the tedious dual-compilation model, the dif...
Dehao Chen, Neil Vachharajani, Robert Hundt, Shih-...