333 search results - page 8 / 67 » EXACT: algorithm and hardware architecture for an improved A... |
CHES
2009
Springer
14 years 9 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
DSD
2008
IEEE
13 years 10 months ago
2008
IEEE
The aim of this work is to present a method for rounding quadratically converging algorithms that improves their performance. This method is able to reduce significantly the numbe...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved lo...