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ICCAD
2004
IEEE
87views Hardware» more  ICCAD 2004»
14 years 6 months ago
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
V. Seth, Min Zhao, Jiang Hu
CVPR
2010
IEEE
14 years 5 months ago
Parallel Graph-cuts by Adaptive Bottom-up Merging
Graph-cuts optimization is prevalent in vision and graphics problems. It is thus of great practical importance to parallelize the graph-cuts optimization using today’s ubiquitou...
Jiangyu Liu, Jian Sun
DATE
2009
IEEE
151views Hardware» more  DATE 2009»
14 years 4 months ago
pTest: An adaptive testing tool for concurrent software on embedded multicore processors
—More and more processor manufacturers have launched embedded multicore processors for consumer electronics products because such processors provide high performance and low powe...
Shou-Wei Chang, Kun-Yuan Hsieh, Jenq Kuen Lee
IPPS
2009
IEEE
14 years 4 months ago
Scaling communication-intensive applications on BlueGene/P using one-sided communication and overlap
In earlier work, we showed that the one-sided communication model found in PGAS languages (such as UPC) offers significant advantages in communication efficiency by decoupling d...
Rajesh Nishtala, Paul Hargrove, Dan Bonachea, Kath...
IPPS
2009
IEEE
14 years 4 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...