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IEEEPACT
2009
IEEE
14 years 2 months ago
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
Qingda Lu, Christophe Alias, Uday Bondhugula, Thom...
DAC
2007
ACM
14 years 8 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
BMCBI
2006
128views more  BMCBI 2006»
13 years 7 months ago
Rank-statistics based enrichment-site prediction algorithm developed for chromatin immunoprecipitation on chip experiments
Background: High density oligonucleotide tiling arrays are an effective and powerful platform for conducting unbiased genome-wide studies. The ab initio probe selection method emp...
Srinka Ghosh, Heather A. Hirsch, Edward A. Sekinge...
AINA
2007
IEEE
14 years 1 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
ICCAD
2005
IEEE
134views Hardware» more  ICCAD 2005»
14 years 1 months ago
Fast thermal simulation for architecture level dynamic thermal management
As power density increases exponentially, runtime regulation of operating temperature by dynamic thermal managements becomes necessary. This paper proposes a novel approach to the...
Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, ...