338 search results - page 50 / 68 » Effective Lower Bounding Techniques for Pseudo-Boolean Optim... |
ISPD
1998
ACM
14 years 3 days ago
1998
ACM
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
IJCAI
2007
13 years 9 months ago
2007
The PDDL3 specifications include soft goals and trajectory constraints for distinguishing highquality plans among the many feasible plans in a solution space. To reduce the compl...
AI
2008
Springer
13 years 8 months ago
2008
Springer
The current best conformant probabilistic planners encode the problem as a bounded length CSP or SAT problem. While these approaches can find optimal solutions for given plan leng...