116 search results - page 15 / 24 » Effective Software Self-Test Methodology for Processor Cores |
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
ICC
2009
IEEE
14 years 2 months ago
2009
IEEE
—We consider a new generation of COTS Software Routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact o...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
CASES
2003
ACM
13 years 11 months ago
2003
ACM
Processors such as StrongARM and memory such as SDRAM enable efficient execution of multiple loads and stores in a single instruction. This is particularly useful in connection wi...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...