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MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
14 years 27 days ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
VISUALIZATION
1992
IEEE
13 years 11 months ago
Display of Scientific Data Structures for Algorithm Visualization
algorithms as networks of modules. The data flow architecture is popular because of the flexibility of mixing calculation modules with display modules, and because of its easy grap...
William L. Hibbard, Charles R. Dyer, Brian E. Paul
VEE
2010
ACM
327views Virtualization» more  VEE 2010»
14 years 2 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova
ICPP
2006
IEEE
14 years 1 months ago
Data Transfers between Processes in an SMP System: Performance Study and Application to MPI
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
Darius Buntinas, Guillaume Mercier, William Gropp
KCAP
2005
ACM
14 years 1 months ago
Estimating similarity among collaboration contributions
The need for collaboration arises in many activities required for effective problem solving and decision making. We are developing Angler, a web-services tool that supports collab...
Kenneth S. Murray, John D. Lowrance, Douglas E. Ap...