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MICRO
2003
IEEE
128views Hardware» more  MICRO 2003»
14 years 22 days ago
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
Stefanos Kaxiras, Georgios Keramidas
25
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ANCS
2007
ACM
13 years 11 months ago
Towards high-performance flow-level packet processing on multi-core network processors
There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection...
Yaxuan Qi, Bo Xu, Fei He, Baohua Yang, Jianming Yu...
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 1 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
QSHINE
2005
IEEE
14 years 1 months ago
Retransmission Strategies for Wireless Connections with Resource-Limited Devices
Protocols designed to provide error-free communications over lossy links, at both data link and transport layers, commonly employ the idea of sliding windows, which is based on th...
Lavy Libman
SIGMETRICS
2008
ACM
113views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Layered interval codes for tcam-based classification
Ternary content-addressable memories (TCAMs) are increasingly used for high-speed packet classification. TCAMs compare packet headers against all rules in a classification database...
Anat Bremler-Barr, David Hay, Danny Hendler, Boris...