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» Efficient Backtracking Instruction Schedulers
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DATE
2008
IEEE
110views Hardware» more  DATE 2008»
14 years 1 months ago
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
One of the upcoming challenges in embedded processing is to incorporate an increasing amount of adaptivity in order to respond to the multifarious constraints induced by today’s...
Lars Bauer, Muhammad Shafique, Stephanie Kreutz, J...
ISCAS
1999
IEEE
113views Hardware» more  ISCAS 1999»
13 years 11 months ago
Energy efficient software through dynamic voltage scheduling
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
Gangadhar Konduri, James Goodman, Anantha Chandrak...
PPOPP
1990
ACM
13 years 11 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
AAAI
1994
13 years 8 months ago
Solution Reuse in Dynamic Constraint Satisfaction Problems
Many AI problems can be modeled as constraint satisfaction problems (CSP), but many of them are actually dynamic: the set of constraints to consider evolves because of the environ...
Gérard Verfaillie, Thomas Schiex
ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
13 years 11 months ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...