Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and manycore microprocessors have the potential to offer scalable perf...
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
Our research goal is to retarget image processing programs written in sequential languages (e.g., C) to architectures with data-parallel processing capabilities. Image processing ...
Lewis B. Baumstark Jr., Murat Guler, Linda M. Will...