101 search results - page 11 / 21 » Efficient Cross-Validation in ILP |
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we present a general and an efficient algorithm for automatic selection of new application-specific instructions under hardware resources constraints. The instructi...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—In this paper, we propose a multi-task mapping/scheduling technique for heterogeneous and scalable MPSoC. To utilize the large number of cores embedded in MPSoC, the proposed te...
MICRO
1996
IEEE
13 years 11 months ago
1996
IEEE
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP)...
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
RECOMB
2002
Springer
14 years 7 months ago
2002
Springer
There are many critical situations when one needs to rapidly identify an unidentified pathogen from among a given set of previously sequenced pathogens. DNA or RNA hybridization c...