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DFT
2003
IEEE
64views VLSI» more  DFT 2003»
15 years 10 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
142
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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 10 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
DAC
2003
ACM
15 years 10 months ago
Fast timing-driven partitioning-based placement for island style FPGAs
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
SIGUCCS
2003
ACM
15 years 10 months ago
Deep in budget restraints: return on investment (ROI)
The University of Missouri–Columbia’s Information and Access Technology (IAT) Services division’s InfoTech Training department measures IT training using the return on inves...
Terry Robb, Joleen Pfefer
IEEEPACT
2002
IEEE
15 years 9 months ago
Eliminating Exception Constraints of Java Programs for IA-64
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komats...