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» Efficient Design Error Correction of Digital Circuits
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DAC
2010
ACM
14 years 9 hour ago
Scalable specification mining for verification and diagnosis
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
Wenchao Li, Alessandro Forin, Sanjit A. Seshia
ICCD
1997
IEEE
87views Hardware» more  ICCD 1997»
14 years 27 days ago
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits
Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions ...
Fu-Chiung Cheng
DAC
2007
ACM
14 years 9 months ago
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting
The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today's most successful response surface methods limit us to lo...
Amith Singhee, Rob A. Rutenbar
UIST
2006
ACM
14 years 2 months ago
CueTIP: a mixed-initiative interface for correcting handwriting errors
With advances in pen-based computing devices, handwriting has become an increasingly popular input modality. Researchers have put considerable effort into building intelligent rec...
Michael Shilman, Desney S. Tan, Patrice Simard
IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
14 years 2 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne