303 search results - page 20 / 61 » Efficient Design Error Correction of Digital Circuits |
ITC
1998
IEEE
14 years 29 days ago
1998
IEEE
ABSTRACT - A multiple pass A/D conversion technique is proposed for mixed-signal test applications. Only a single on-chip comparator and sample-and-hold circuit is required to digi...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit’s intrinsic errors, such as overflow. A method is prop...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
POPL
2007
ACM
14 years 9 months ago
2007
ACM
We propose a new technique for hardware synthesis from higherorder functional languages with imperative features based on Reynolds's Syntactic Control of Interference. The re...
WCE
2007
13 years 10 months ago
2007
—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-n...