303 search results - page 23 / 61 » Efficient Design Error Correction of Digital Circuits |
TCAD
2008
13 years 8 months ago
2008
Abstract--Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and d...
ASYNC
1998
IEEE
14 years 1 months ago
1998
IEEE
Analogue to digital (A-D) converters with a xed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time fo...
FPL
2008
Springer
13 years 10 months ago
2008
Springer
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
ICCAD
2000
IEEE
14 years 9 days ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
VLSID
1999
IEEE
14 years 1 months ago
1999
IEEE
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...