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» Efficient Design Error Correction of Digital Circuits
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TVLSI
2008
140views more  TVLSI 2008»
13 years 8 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
14 years 2 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
14 years 9 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
ISCAS
2007
IEEE
95views Hardware» more  ISCAS 2007»
14 years 3 months ago
An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters
—This paper presents an incomplete settling design technique for switched-capacitor pipelined analog-to-digital converters (ADCs) to improve conversion rate. An improved multiply...
Fule Li, Zhihua Wang, Dongmei Li
CORR
2010
Springer
152views Education» more  CORR 2010»
13 years 6 months ago
Fault Tolerant Variable Block Carry Skip Logic (VBCSL) using Parity Preserving Reversible Gates
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...