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» Efficient Design Error Correction of Digital Circuits
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TVLSI
2010
13 years 3 months ago
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
Shu Li, Tong Zhang
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
14 years 2 months ago
A differential switched-capacitor amplifier with programmable gain and output offset voltage
The design of a low-power differential switched-capacitor amplifier for processing a fully-differential input signal coming from a pressure sensor interface is reported. The circu...
Fabio Lacerda, Stefano Pietri, Alfredo Olmos
DAC
2007
ACM
14 years 9 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
ICASSP
2011
IEEE
13 years 14 days ago
Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard
Bit-Interleaved Coded Modulation (BICM) offers a significant improvement in error correcting performance for coded modulations over fading channels compared to the previously exis...
Meng Li, Charbel Abdel Nour, Christophe Jég...
ICCAD
2008
IEEE
115views Hardware» more  ICCAD 2008»
14 years 5 months ago
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...
Mohammad Ghasemazar, Massoud Pedram