303 search results - page 40 / 61 » Efficient Design Error Correction of Digital Circuits |
ITC
2000
IEEE
14 years 1 months ago
2000
IEEE
We describe logic synthesis techniques for designing diverse implementations of combinational logic circuits in order to maximize the data integrity of diverse duplex systems in t...
ARVLSI
1997
IEEE
14 years 29 days ago
1997
IEEE
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...
FPGA
2009
ACM
14 years 1 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
TCOM
2008
13 years 8 months ago
2008
This paper proposes a general and systematic code design method to efficiently combine constrained codes with parity-check (PC) codes for optical recording. The proposed constraine...
ISCA
2010
IEEE
14 years 22 days ago
2010
IEEE
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...