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» Efficient Exact Two-Level Hazard-Free Logic Minimization
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ASYNC
2001
IEEE
136views Hardware» more  ASYNC 2001»
13 years 11 months ago
Efficient Exact Two-Level Hazard-Free Logic Minimization
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
Chris J. Myers, Hans M. Jacobson
ASYNC
1998
IEEE
100views Hardware» more  ASYNC 1998»
13 years 11 months ago
An Implicit Method for Hazard-Free Two-Level Logic Minimization
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...
Michael Theobald, Steven M. Nowick
DAC
1996
ACM
13 years 11 months ago
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic
-- We present a new heuristic algorithm for hazard-free minimization of two-level logic. On nearly all examples, the algorithm finds an exactly minimum-cost cover. It also solves s...
Michael Theobald, Steven M. Nowick, Tao Wu
INTEGRATION
2008
89views more  INTEGRATION 2008»
13 years 7 months ago
Exact ESCT minimization for functions of up to six input variables
In this paper an efficient algorithm for the synthesis and exact minimization of ESCT(Exclusive or Sum of Complex Terms) expressions for Boolean functions of at most six variables...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...
VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
13 years 11 months ago
Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms
Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper, we prese...
M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale