283 search results - page 19 / 57 » Efficient FPGA hardware development: A multi-language approa... |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
SIGARCH
2010
13 years 2 months ago
2010
We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources pr...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant thr...
TCAD
2008
13 years 7 months ago
2008
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...